In flash memories which are electrically rewritable non-volatile semiconductor memory devices, N-channel type memory cells are mainly used. The N-channel type memory cells perform writing by injecting channel hot electrons, and thus their reliability decreases as the miniaturization thereof proceeds. Accordingly, use of P-channel type memory cells is considered as an alternative technology.
FIG. 19 is a diagram illustrating a structural example of a memory cell array using P-channel type memory cells. FIG. 20 is a diagram illustrating an example of voltage setting in each operation in the semiconductor memory device having the P-channel type memory cells. In a read operation, −3 V is applied to a selected word line WL, 1.8 V is applied to a non-selected word line WL, 1.8 V is applied to a source line SRC, and 1.8 V is applied to an N-type well NW. In an erase operation, −9 V is applied to each word line WL of the block (sector) to be erased at once, 9 V is applied to the source line SRC, and 9 V is applied to the N-type well NW. Note that in the erase operation, bit lines BL of the block (sector) to be erased are in a high impedance (HiZ) state. In a program operation, 9 V is applied to a selected word line WL, 0 V is applied to a non-selected word line WL, 1.8 V is applied to the source line SRC, and 5 V is applied to the N-type well NW. Further, in the program operation, 0 V is applied to a bit line BL connected to memory cells to be written, and 2.4 V is applied to a bit line BL connected to memory cells which are not to be written.
Thus, for the memory cells of P-channel type, there is known a method to perform writing by injecting hot electrons generated by inter-band tunneling in the vicinity of the drain by applying a voltage to the N-type well and the gate. For example, as illustrated in FIG. 19, when writing to a memory cell 111 having a gate connected to a word line WLA and a drain connected to a bit line BLA is performed, a voltage Vwla to be applied to the selected word line WLA is 9 V, and a voltage Vbla to be applied to the selected bit line BLA is 0 V. Further, a voltage Vwlb to be applied to the non-selected word line WLB is 0 V, and a voltage Vblb to be applied to the non-selected bit line BLB is 2.4 V. Note that a source voltage Vs to be applied to the sources of the respective transistors of the memory cells 111, 112, 113, 114 is 1.8 V, and a voltage Nwell to be applied to the N-type well is 5 V.
By performing the erase operation and the program operation by applying voltages as illustrated in FIG. 20, the threshold voltages of the P-channel type memory cells are controlled as illustrated in FIG. 21. The threshold voltage of a memory cell with a bit in a program state is higher than the threshold voltage of a memory cell with a bit in an erase state. The threshold voltage of the memory cell with a bit in a program state is higher than a program verify level, and the threshold voltage of the memory cell with a bit in an erase state is lower than an erase verify level. In the read operation, whether the data stored in a memory cell is 0 or 1 is judged by judging whether the threshold voltage of the memory cell is higher or lower than a read level set between the program verify level and the erase verify level.
There has been disclosed a technology to divide a storage area into plural blocks in a flash memory, the sources of memory cells are connected in common in every block, and a source voltage is given thereto (see, for example, Patent Documents 1, 2). There has also been disclosed a technique to change the source voltage depending on whether it is a selected block or a non-selected block (see, for example, Patent Document 1).    [Patent Document 1] Japanese Laid-open Patent Publication No. 06-314495    [Patent Document 2] Japanese Laid-open Patent Publication No. 05-266220
When the P-channel type memory cells are used and writing is performed by applying a voltage to the N-type well and the gate as described above, memory cells connected to the same bit line as the memory cell to be written as well as memory cells connected to the same word line thereof suffer disturbance during the writing. In the example illustrated in FIG. 19, the other memory cell 112 connected to the word line WLA to which the memory cell 111 to be written is connected suffers gate disturb. The other memory cell 113 connected to the bit line BLA to which the memory cell 111 to be written is connected suffers drain disturb.
FIG. 22 is a diagram illustrating a change in the threshold voltage of a memory cell due to the gate disturb. FIG. 23 is a diagram illustrating a change in the threshold voltage of a memory cell due to the drain disturb. In FIG. 22 and FIG. 23, the horizontal axis indicates the time in which the transistor of the memory cell suffers the gate disturb or the drain disturb, and the vertical axis indicates the maximum threshold voltage in a threshold distribution of memory cells with a bit in an erase state.
As illustrated in FIG. 22, in the memory cell, when the time of suffering the gate disturb becomes long, there occurs a shift in the threshold voltage of the memory cell due to the gate disturb, and the threshold voltage increases. As illustrated in FIG. 23, in the memory cell, when the time of suffering the drain disturb becomes long, there occurs a shift in the threshold voltage of the memory cell due to the drain disturb, and the threshold voltage increases. When the threshold voltage of the memory cell with a bit in an erase state becomes too high, there arises a possibility that it is judged as a bit in a program state during reading.
Here, by increasing the source voltage during the program operation, the change of the threshold voltage of the memory cell due to the gate disturb becomes, for example, as illustrated from a solid line VL11 to a dashed line VL12, and the time until the threshold voltage begins to increase becomes long. That is, resistance to the gate disturb improves. However, when the source voltage is increased during the program operation, in other memory cells connected to the same bit line as the memory cell to be written, leak currents from the sources of the memory cell transistors to the bit line increase.